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Kind code of ref document: A duobinary-to-binary signal converter includes a pair of comparators coupled to a logic gate. Each comparator receives a copy of a duobinary-encoded analog signal applied to the converter and is designed to generate a binary output based on the comparison of the magnitude of the received signal with a corresponding threshold voltage.
The outputs of the comparators are fed into the logic gate, which generates a binary sequence corresponding to the duobinary-encoded signal. The present invention relates to communication equipment and, more specifically, to equipment for decoding duobinary signals. Duobinary signaling was introduced in the s and since then has found numerous applications in communication systems.
The principle of duobinary signaling is explained, for example, in an article by A. A signal corresponding to one of these levels i. A duobinary signal is typically generated from a corresponding binary signal using certain transformation rules. Although both signals carry the same information, the bandwidth of the duobinary signal may be reduced by a factor of 2 compared to that of the binary signal at the expense of signal-to-noise ratio.
In addition, the duobinary signal may be constructed such that it has certain inter-symbol correlation ISC data, which can be used to implement an error-correction algorithm at the receiver. One such transformation described in the above-cited Lender article is as follows. More specifically, when i is odd, the polarity of b m is the same as the polarity of b m-i ; and, when i is even, the polarity of b m is the opposite of the polarity of b m-i.
Reconstruction of a k from a known b k is relatively straightforward. Table 1 reproduces an example given in the Lender article to further illustrate the above-described transformation.
However, one problem with such a converter is that, at relatively high data transmission rates, e. Problems in the prior art are addressed, in accordance with the principles of the present invention, by a duobinary-to-binary signal converter including, in one embodiment, a pair of comparators coupled to a logic gate.
According to one embodiment, the present invention is a device, comprising: According to another embodiment, the present invention is a method of signal processing, comprising: A comparing magnitude of an electrical signal with first and second threshold voltages to generate first and second binary values; B applying a logic function to the first and second binary values to generate a third binary value; and C repeating steps A and B to generate a sequence of third binary values, wherein: According to yet another embodiment, the present invention is a data transmission system designed to use duobinary signaling, the system including a device comprising: Other aspects, features, and benefits of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which: Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention.
The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
More specifically, system is designed to transmit information corresponding to an input binary data sequence, c k , e. Sequence c k is recovered at the output of system as sequence c' k.
At the transmitter end, system has a precoder designed to introduce inter-symbol correlation ISC data into sequence c k. More details on representative circuits that can serve as precoder and encoder in system can be found, for example, in U. Transmission channel has a transmitter coupled to one end of a transmission link and an optional receiver coupled to the other end of that transmission link none of which are explicitly shown in Fig.
Based on duobinary sequence d k , the transmitter generates an appropriate communication signal and applies that signal to the transmission link. At the remote end of the link, the receiver if any receives the communication signal and generates a corresponding analog signal denoted as s t in Fig. In one embodiment, channel has i a transmitter comprising a laser coupled to an electro-optical modulator and ii a receiver comprising a photodiode, said transmitter and receiver coupled to an optical fiber.
In another embodiment, channel has a radio-frequency RF transmitter and an RF receiver communicating over the wireless medium. In yet another embodiment, channel has an electrical waveform generator coupled to a conductor, e. A decoder reverses the coding of precoder to generate sequence c' k. Decoder may be designed to utilize the ISC of sequence p k to detect and correct errors in sequence p' k.
A representative implementation of decoder is described in U. Converter includes a full-wave rectifier FWR coupled to a slicer FWR converts signal s t into rectified signal s' t , in which polarity of the negative waveforms is reversed while the positive waveforms remain substantially unchanged. Exemplary embodiments of FWR can be found in U. Slicer then processes signal s' t as known in the art to produce sequence p' k. In particular, when the wavelength of RF signals in FWR is comparable to certain circuit dimensions, parasitic circuit effects adversely affect the performance of the FWR and thereby converter As a result, designing converter that works well at relatively high bit rates and is also relatively small, power-efficient, and inexpensive may be difficult.
In addition, converter can be adapted in a relatively straightforward fashion to work at even higher bit rates and lends itself to relatively easy incorporation into an integrated device e. Copy s a t is applied to an inverting input of a first comparator a, whose non-inverting input receives a first threshold voltage, V 1.
Similarly, copy s b t is applied to a non-inverting input of a second comparator b, whose inverting input receives a second threshold voltage, V 2. The output, x , of each comparator is a digital signal generated as follows.
The output of each comparator is applied to an exclusive-OR XOR gate , which generates sequence p' k. The signal trace shown in Fig. Table 2 illustrates the operation of converter configured in accordance with Fig. Converter is similar to converter Fig. However, one difference between converters and , is that, in converter , each signal copy is applied to a non-inverting input of the corresponding comparator Table 3 illustrates the operation of converter configured in accordance with Fig.
Advantageously, converters of the present invention adapted for relatively high bit rates do not require complex microwave-matching circuits of prior-art converters e. While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense.
Although converters of the present invention are described as receiving analog signals, they can similarly be configured to receive digital signals. A converter of the invention may be based on a pair of comparators whose configuration may be differently and appropriately selected.
A logic gate may be implemented as a combination of suitable logic elements as known in the art. Transmission system employing a converter of the invention may be configured to operate with or without data precoding and the corresponding decoding.
Although exemplary data rates e. Various modifications of the described embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the principle and scope of the invention as expressed in the following claims.
Although the steps in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.
The device of claim 1, wherein: The device of claim 1, further comprising a splitter adapted to receive the input signal and generate the first and second copies, wherein: The device of claim 4, wherein: A method of signal processing, comprising: A comparing magnitude of an electrical signal with first and second threshold voltages to generate first and second binary values;.
B applying a logic function to the first and second binary values to generate a third binary value; and. C repeating steps A and B to generate a sequence of third binary values, wherein: The method of claim 7, wherein, for step A: A data transmission system designed to use duobinary signaling, the system including a device comprising: US USA1 en Method, transmitter and receiver device for transmitting a binary digital transmit signal over an optical transmission link.
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